Semiconductor devices include many electronic components, such as transistors, resistors, capacitors, and diodes. Semiconductor devices are designed by transforming logical or circuit descriptions of the semiconductor device components into geometric descriptions, called design layouts. Design layouts often describe the behavioral, architectural, functional, and structural attributes of the semiconductor device. Electronic design automation (“EDA”) applications are typically used to create the design layouts. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts.
Fabrication foundries manufacture semiconductor devices based on the design layouts using photolithographic processes. To fabricate a semiconductor device, photomasks are created using the design layout as a template. The photomasks contain the various geometries (i.e., features) of the semiconductor device design layout. Through sequential use of the various photomasks corresponding to a given semiconductor device in a fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall semiconductor device and the circuits within the design layout.
Some features cannot be photolithographically printed with a conventional single exposure process. Therefore, fabrication processes have implemented a multiple exposure photolithographic process, such as a double patterning technique (DPT). In DPT, the design layout is decomposed to a first decomposed layout and a second decomposed layout. Existing decomposition tools for decomposing layouts into one or more decomposed layouts are often rule based and proceed on a pattern by pattern (i.e., geometry by geometry) basis. After decomposition to the first and second masks, post-decomposition rule checks including a Design Rule Check and a Mask Rule Check are performed to determine whether the proposed first and second masks are rule compliant. A Mask Data Preparation (MDP) operation is then performed to yield a manufacturable mask layout. Despite the testing performed, some decomposed layouts that comply with post-decomposition rule checks yield mask layouts with printability failure points, especially at the presence of process variation.
Accordingly, it is desirable to provide improved methods for fabricating semiconductor devices using multiple patterning lithographic techniques. Also, it is desirable to provide methods for decomposing design layouts for multiple patterning lithographic techniques that avoid printability failure points in decomposed layouts. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.